1. Field of the Invention
The present invention relates to the field of integrated circuits and, more particularly, to a buffer management system for use with such devices.
2. Description of the Related Art
Data processing systems, such as communication systems, typically must perform functions relating to the storage, reordering, and forwarding of packets of data. Often, the packets of data are stored in a random access memory (RAM) that is divided into a plurality of different buffers. To support the different processing needs of the data processing system, packets of data are read out from the buffers in a different order or sequence than the order in which the packets of data were initially written to the buffers.
In illustration, a data processing system may require that packets be classified into several different categories. Within each category, packets may need to be processed in chronological order. To accomplish this sort of processing, a priority-based system, or subsystem, that is capable of tracking buffers is needed. Typically, such a system is implemented using a plurality of parallel data structures of arrays of registers. The registers are used to store a status for each buffer as well as metadata pertaining to the contents of each respective buffer.
FIG. 1 is a schematic diagram illustrating a conventional buffer management system 100 that supports non-sequential access to buffers. As shown, buffer management system 100 can include a set of registers 105 and a set of buffers 110. The buffers 110 typically are implemented within RAM. Unlike the buffers 110, each of the registers 105 is implemented using dedicated hardware, not in RAM. The buffer management system 100 facilitates non-sequential access to individual ones of the buffers 110 through the use of registers 105 as well as register-based priority encoding logic depicted as priority logic 115 and 120. The priority logic 115 and 120, as indicated in FIG. 1, further includes a multiplexer and a de-multiplexer respectively.
The registers 105, in combination with the priority logic 115 and 120, track which buffers 110 are available for writing and determine the order in which data is read from the buffers based upon constraints of the particular application with which the buffer management system 100 is used. To select the next buffer to be sequenced, or used, it is necessary to perform logical operations on the entire contents of all of the registers 105. Once a selection is made, additional logical operations must be performed to multiplex the metadata stored within the registers so that the buffer and the metadata associated with that buffer remain associated as each is moved along a data path of a circuit.
It should be appreciated that a system as described with reference to FIG. 1 can include a large number of buffers, with each having a corresponding register for tracking purposes. Buffer management systems of this variety are implemented as large structures of combinatorial logic. Such systems require significant resources within a programmable logic device, i.e. a field programmable gate array, to properly sequence the buffers. Further, conventional buffer management systems tend to be slow in terms of performance due to the significant number of calculations that must be performed, i.e. multiplexing the metadata and performing logic operations across the contents of all registers.
In consequence, buffer management systems of the variety described with reference to FIG. 1 do not operate at the speeds necessary for passing high-bandwidth data. These systems are not considered to be flexible in terms of the number of buffers that are supported since increasing the number of buffers requires rewriting the control logic. Increasing the number of buffers also results in an even wider control path as measured in terms of the number of parallel buffers used. This in turn requires a greater number of logic levels, further decreasing the speed at which the design may operate.
It would be beneficial to implement a buffer management system that overcomes the limitations described above.